For embedded systems that are used in real time environments
correct and precise estimations of the worst-case execution times
(WCET) of their tasks are needed to guarantee that actions take place
before a mandatory dead-line.
The problem of finding a tight WCET estimate for a given problem is
becoming more and more complicated as hardware becomes more and more
complex. Caches and Pipelines represent one of the hardest
challenges. Today's embedded systems start to use the same advanced
speed-up mechanisms as desktop microprocessors including caches.
The goal of Transferbereich 14 is the development of a
prototype system for computing the WCET of modern processors. Our
primary target architectures are the Motorola ColdFire 5307
and the Motorola PowerPC 755.