Jörg Herter

2007, Israel

Research Interests

  • Static Program Analysis
  • Dynamic Memory Allocation & WCET Analyses
  • Shape Analysis

Projects

CAMA---Cache-Aware Dynamic Memory Allocation

CAMA is a novel, cache-aware memory allocator. It strives to alleviate predictability issues with existing dynamic memory allocators that forbid their use within hard real-time systems for which tight bounds on the worst-case execution time (WCET) must be statically derivable.
Predictability and hence compatibility with WCET analyses is achieved as follows. Allocation requests (may) include the desired starting cache set of returned memory blocks. Free blocks are managed in segregated free lists to allow for constant look-up times and hence constant response times. The allocator uses cache-aware splitting and coalescing techniques for blocks exceeding a minimum block size to keep external fragmentation low. Internal fragmentation is reduced by using a multi-layered segregated list approach.

AVACS---Automatic Verification and Analysis of Complex Systems


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Publications

Conference Papers

  1. PRADA: Predictable Allocations by Deferred Actions
    F. Haupenthal, and J. Herter
    13th International Workshop on Worst-Case Execution Time Analysis, 2013. [doi]  [url]  [pdf]  [bib]
  2. CAMA: A Predictable Cache-Aware Memory Allocator
    J. Herter, P. Backes, F. Haupenthal, and J. Reineke
    Proceedings of the 23rd Euromicro Conference on Real-Time Systems (ECRTS '11), 2011. [pdf]  [bib]
  3. Cache Analysis in Presence of Pointer-Based Data Structures
    T. Dudziak, and J. Herter
    Proceedings Work-In-Progress Session of the 23rd Euromicro Conference on Real-Time Systems, 2011. [pdf]  [bib]
  4. Static Timing Analysis for Hard Real-Time Systems
    R. Wilhelm, S. Altmeyer, C. Burguière, D. Grund, J. Herter, J. Reineke, B. Wachter, and S. Wilhelm
    VMCAI, 2010. [doi]  [bib]
  5. Precomputing Memory Locations for Parametric Allocations
    J. Herter, and S. Altmeyer
    Proceedings of 10th International Workshop on Worst-Case Execution Time (WCET) Analysis, 2010. [pdf]  [pdf]  [slides]  [bib]
  6. Allocation-Site Aware Shape Analysis and Applications in Hard Real-Time Systems
    J. Herter
    Proceedings of JRWRTC, 2010. [pdf]  [bib]
  7. Making Dynamic Memory Allocation Static To Support WCET Analyses
    J. Herter, and J. Reineke
    Proceedings of 9th International Workshop on Worst-Case Execution Time (WCET) Analysis, 2009. [pdf]  [slides]  [bib]
  8. CAMA: Cache-Aware Memory Allocation for WCET Analysis
    J. Herter, J. Reineke, and R. Wilhelm
    Proceedings Work-In-Progress Session of the 20th Euromicro Conference on Real-Time Systems, 2008. [pdf]  [slides]  [bib]

MSc Theses

  1. Towards Shape Analysis of B-Trees
    J. Herter
    Universität des Saarlandes, 2008. [pdf]  [bib]

Older publications (prior to 2008) can be found on my member page at the HTWdS .

Selected Talks

  • 5-minutes talk on CAMA given at the WiP session of the ECRTS'08 in Prague. [ pdf ]

Posters

  • "Precise WCET Analysis in the Presence of Dynamic Memory Allocation", exhibited at the EDAA PhD Forum 2009, Nice 2009. [ pdf ]
  • "Cache-Aware Memory Allocation for WCET Analysis", exhibited at the WiP discussion forum of the ECRTS, Prague 2008. [ pdf ]

Attended Conferences, Workshops, and Seminars

Teaching

My courses given at the HTWdS (Saarland's University of Applied Sciences) and the ASW (Saarland's University of Cooperative Education) are listed here.

Address

Jörg Herter
FR. 6.2 - Informatik, Gebäude E1 3, Raum 404
Universität des Saarlandes
Postfach 15 11 50
66041 Saarbrücken
Germany

Tel.: +49 - 681 - 302 5573
Fax : +49 - 681 - 302 3065
Mail: jherter (at) cs (dot) uni-saarland (dot) de

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